SK hynix Introduces H-TPU to Enhance SSD Controllers and Manage Rising Performance Demands

SK hynix is innovating in the SSD controller space by introducing an in-house designed core called the Hynix Transaction Processing Unit (H-TPU). Unlike traditional CPU cores, the H-TPU is tailored for less power-hungry, routine tasks associated with SSD operations, effectively aiming to reduce the overall workload on general-purpose processors as SSD performance accelerates.

As described by Koo In-jae, the company's VP of system-on-chip (SoC) design, during the recent International SoC Design Conference (ISOCC 2026), current SSD controller CPUs are nearing their limits in terms of power and spatial efficiency. With PCIe bandwidth experiencing a consistent doubling each generation, Koo highlighted that the capabilities of controller CPUs simply can't keep pace. This escalating demand for input/output operations per second (IOPS) particularly raises challenges in products targeting enterprise solutions.

The H-TPU Architecture

The H-TPU is engineered as a compact, power-efficient alternative, consuming only 2.5% of a conventional CPU’s power while occupying just 4% of the area of a standard core. Each H-TPU operates within a four-stage, in-order execution pipeline tailored for processing read and write commands and managing essential data operations such as metadata and buffer control.

SK hynix’s strategy breaks the traditional monolithic CPU architecture into clusters of specialized TPUs, each dedicated to a specific task. This architecture contrasts starkly with competitors like Marvell, which increases core counts to manage performance demands. For instance, Marvell employs 12 Cortex-R82 cores alongside other Cortex cores in its PCIe 6.0 Bravera SC6 controller, an increase compared to the architecture used in its PCIe 5.0 counterpart.

By distributing tasks across numerous small H-TPUs, SK hynix intends to optimize both power consumption and efficiency. The H-TPU clusters collectively handle over 100 distinct storage functions, a substantial increase over the capabilities of a singular CPU. While the primary CPU still manages error recovery and storage policies, the bulk of routine processing can be offloaded to the H-TPUs, which can enter a low-power idle mode when not in use.

Design Philosophy and Functionality

Although the H-TPU's approach of splitting tasks is not entirely novel—products like Phison’s CoXProcessor have long utilized specialized cores—SK hynix expands this concept significantly. Its development could enhance the performance of enterprise storage solutions while adhering to stringent energy efficiency requirements.

A technical detail worth noting is the emphasis on dedicated compiler tools for customized code development. This allows for greater flexibility in programming and optimizing tasks specifically suited for the H-TPU's architecture.

SK hynix has substantiated its H-TPU design with several patents that outline configurations separating management functions among small processors. For example, one patent delineates I/O operations passing through various specialized cores, ensuring minimal intervention from the primary CPU while maintaining a seamless data processing pipeline.

Future Directions and Applications

The implementation of H-TPUs is set to extend across SK hynix's NAND products, including upcoming enterprise-grade SSD controllers. This is particularly relevant as manufacturers seek to meet the insatiable demand for higher-performing SSDs, especially in contexts like AI-driven data centers where workloads are expected to grow exponentially.

Upcoming technologies such as high-bandwidth flash (HBF) memory stacks will also leverage H-TPUs. With potential read/write ratios soaring to around 300,000 to 1 for AI inference tasks, the use of H-TPUs ensures that data flows can be optimized, thereby mitigating the latency that traditionally plagues SSD operations.

Despite the promise of H-TPU's design, it hasn’t yet been integrated into a production-level enterprise SSD controller. SK hynix is keen to push boundaries as the industry progresses towards PCIe 7.0 and 8.0 protocols, projected to deliver even greater performance enhancements in the future.

Thus, as storage demands continuously evolve, SK hynix is taking proactive steps to integrate the H-TPU into their SSD architecture, indicating a shift towards more specialized processing designs that could redefine the limits of SSD performance while promoting energy efficiency.

Conclusion

The evolution to H-TPUs marks a pivotal shift in the SSD controller market, as manufacturers grapple with the complexities of rising speeds and performance demands. Looking ahead, the integration of H-TPUs across existing and forthcoming products could greatly alter the competitive dynamics of high-performance storage solutions, particularly as AI-centric Server demands continue to challenge traditional architectures.